Load your constraints to define clock speed, input delays, and output loads.
set_fix_multiple_port_nets -all -buffer_constants
Now, let's walk through the in DC.
These constraints simulate the physical environment where the chip will operate. synopsys design compiler tutorial 2021
# Analyze the RTL (Checks for syntax) analyze -format verilog my_design.v sub_module.v # Elaborate (Builds the generic technology-independent design) elaborate my_design # Set the current design context current_design my_design Use code with caution. 4. Applying Constraints (The SDC File)
Before typing a single command, ensure your environment is ready. The 2021 version introduced stricter TCL 8.6 compliance and deprecated some legacy commands.
| Action | Command | |--------|---------| | Check design | check_design | | Show clock | report_clock | | Reset design | remove_design -all | | Change naming rule | define_name_rules ... | | Ungroup hierarchies | ungroup -flatten -all | | Set max area | set_max_area 0 | | Set max fanout | set_max_fanout 20 [current_design] | Load your constraints to define clock speed, input
set_host_options -max_cores 8 compile_ultra -timing -retime
# Maximum transition time (slew rate) set_max_transition 0.5 [current_design]
# Define a clock named 'sys_clk' on port 'clk' with a 10ns period (100 MHz) create_clock -name sys_clk -period 10.0 [get_ports clk] # Model clock uncertainty (skew, jitter, margin) set_clock_uncertainty 0.25 [get_clocks sys_clk] # Model clock transition times set_clock_transition 0.15 [get_clocks sys_clk] Use code with caution. Input and Output Delays # Analyze the RTL (Checks for syntax) analyze
# Assume external chip paths take 30% of clock cycle set_input_delay 3.0 -clock sys_clk [remove_from_collection [all_inputs] [get_ports clk]] set_output_delay 3.0 -clock sys_clk [all_outputs] Use code with caution. Design Environment Constraints
dc_shell> source run_synthesis.tcl
Comprehensive Synopsys Design Compiler Tutorial Synopsys Design Compiler (DC) is the industry-standard tool for RTL synthesis. It translates your Hardware Description Language (HDL) code, such as Verilog or VHDL, into a technology-specific gate-level netlist. This tutorial guides you through the complete synthesis flow using the modern Design Compiler Topographical mode. 1. Introduction to Synthesis Flow